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cy7c1010dv33 2-mbit (256k x 8) static ram cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 001-00062 rev. *c revised october 14, 2010 features pin and function compatible with cy7c1010cv33 high speed ? t aa = 10 ns low active power ? i cc = 90 ma at 10 ns low cmos standby power ? i sb2 = 10 ma 2.0v data retention automatic power down when deselected ttl-compatible inputs and outputs easy memory expansion with ce and oe features available in pb-free 36-pin soj and 44-pin tsop ii packages functional description the cy7c1010dv33 is a high performance cmos static ram organized as 256k words by 8 bits. easy memory expansion is provided by an active low chip enable (ce ), an active low output enable (oe ), and three-state drivers. writing to the device is accomplished by taking chip enable (ce ) and write enable (we ) inputs low. data on the eight i/o pins (i/o 0 through i/o 7 ) is then written into the location specified on the address pins (a 0 through a 17 ). reading from the device is accomplished by taking chip enable (ce ) and output enable (oe ) low while forcing write enable (we ) high. under these conditions, the contents of the memory location specified by the address pins will appear on the i/o pins. the eight input and output pins (i/o 0 through i/o 7 ) are placed in a high impedance state when the device is deselected (ce high), the outputs are disabled (oe high), or during a write operation (ce low, and we low). the cy7c1010dv33 is available in 36-pin soj and 44-pin tsop ii packages with center power and ground (revolutionary) pinout. refer to the cypress application note an1064, sram system guidelines for best practice recommendations. a 0 io 0 io 7 io 1 io 2 io 3 io 4 io 5 io 6 a 1 a 2 a 3 a 4 a 5 a 6 a 7 a 8 a 9 sense amps power down ce we oe a 12 a 13 a 14 a 15 a 16 row decoder column decoder 256k x 8 array input buffer a 10 a 17 a 11 logic block diagram [+] feedback
cy7c1010dv33 document number: 001-00062 rev. *c page 2 of 12 selection guide description ?10 unit maximum access time 10 ns maximum operating current 90 ma maximum cmos standby current 10 ma pin configuration figure 1. 36-pin soj [1] figure 2. 44-pin tsop ii [1] 1 2 3 4 5 6 7 8 9 11 14 31 32 36 35 34 33 12 13 16 15 29 30 18 17 20 19 27 28 25 26 22 21 23 24 nc a 4 a 3 a 2 a 14 a 15 a 12 nc nc a 13 a 5 a 6 a 7 a 1 a 16 a 0 ce io 0 io 1 io 2 io 3 we a 17 a 10 a 9 io 4 io 5 io 6 io 7 oe a 8 v cc v cc gnd gnd a 11 10 1 2 3 4 5 6 7 8 9 11 14 31 32 36 35 34 33 37 40 39 38 12 13 41 44 43 42 16 15 29 30 nc 18 17 20 19 27 28 25 26 22 21 23 24 nc nc nc nc a 4 a 3 a 2 a 14 a 15 a 12 nc nc nc nc a 13 nc nc a 5 a 6 a 7 a 1 a 16 a 0 ce io 0 io 1 io 2 io 3 we a 17 a 10 a 9 io 4 io 5 io 6 io 7 oe a 8 v cc v cc v ss v ss a 11 10 note: 1. nc pins are not connected on the die. [+] feedback
cy7c1010dv33 document number: 001-00062 rev. *c page 3 of 12 maximum ratings exceeding the maximum ratings may impair the useful life of the device. these user guidelines are not tested. storage temperature ................................. ?65 ? c to +150 ? c ambient temperature with power applied ............................................ ?55 ? c to +125 ? c supply voltage on v cc relative to gnd [2] ....?0.5v to +4.6v dc voltage applied to outputs in high z state [2] ................................... ?0.3v to v cc + 0.3v dc input voltage [2] ............................... ?0.3v to v cc + 0.3v current into outputs (low) ........................................ 20 ma static discharge voltage.................................................>2001v (mil-std-883, method 3015) latch up current ..................................................... >200 ma operating range range ambient temperature v cc industrial ?40 ? c to +85 ? c3.3v ? 0.3v electrical characteristics over the operating range parameter description test conditions ?10 unit min max v oh output high voltage v cc = min.; i oh = ?4.0 ma 2.4 v v ol output low voltage v cc = min.; i ol = 8.0 ma 0.4 v v ih input high voltage 2.0 v cc + 0.3 v v il input low voltage [2] ?0.3 0.8 v i ix input leakage current gnd < v i < v cc ?1 +1 ? a i oz output leakage current gnd < v out < v cc , output disabled ?1 +1 ? a i cc v cc operating supply current v cc = max., f = f max = 1/t rc 100 mhz 90 ma 83 mhz 80 66 mhz 70 40 mhz 60 i sb1 automatic ce power-down current ?ttl inputs max. v cc , ce > v ih ; v in > v ih or v in < v il , f = f max 20 ma i sb2 automatic ce power-down current ?cmos inputs max. v cc , ce > v cc ? 0.3v, v in > v cc ? 0.3v, or v in < 0.3v, f = 0 10 ma capacitance tested initially and after any design or process changes that may affect these parameters. parameter description test conditions soj tsop ii unit c in input capacitance t a = 25 ? c, f = 1 mhz, v cc = 3.3v 8 8 pf c out io capacitance 8 8 pf thermal resistance tested initially and after any design or process changes that may affect these parameters. parameter description test conditions soj tsop ii unit ? ja thermal resistance (junction to ambient) still air, soldered on a 3 4.5 inch, four layer printed circuit board 59.17 50.66 ? c/w ? jc thermal resistance (junction to case) 32.63 17.77 ? c/w note 2. v il (min.) = ?2.0v and v ih (max.) = v cc + 2.0v for pulse durations of less than 20 ns. [+] feedback
cy7c1010dv33 document number: 001-00062 rev. *c page 4 of 12 figure 3. ac test loads and waveforms [3] 90% 10% 3.0v gnd 90% 10% all input pulses * capacitive load consists of all components of the test environment rise time: 1 v/ns fall time: 1 v/ns 30 pf* output z = 50 ? 50 ? 1.5v (b) (a) 3.3v output 5 pf (c) r 317 ? r2 351 ? high-z characteristics: note 3. ac characteristics (except high-z) are tested using the load conditions shown in figure (a). high-z characteristics are teste d for all speeds using the test load shown in figure (c). [+] feedback
cy7c1010dv33 document number: 001-00062 rev. *c page 5 of 12 ac switching ch aracteristics over the operating range [4] parameter description ?10 unit min. max. read cycle t power [5] v cc (typical) to the first access 100 ? s t rc read cycle time 10 ns t aa address to data valid 10 ns t oha data hold from address change 3 ns t ace ce low to data valid 10 ns t doe oe low to data valid 5 ns t lzoe oe low to low-z 0 ns t hzoe oe high to high-z [6, 7] 5ns t lzce ce low to low-z [7] 3ns t hzce ce high to high-z [6, 7] 5ns t pu ce low to power-up 0 ns t pd ce high to power-down 10 ns write cycle [8, 9] t wc write cycle time 10 ns t sce ce low to write end 7 ns t aw address set-up to write end 7 ns t ha address hold from write end 0 ns t sa address set-up to write start 0 ns t pwe we pulse width 7 ns t sd data set-up to write end 5 ns t hd data hold from write end 0 ns t lzwe we high to low-z [7] 3ns t hzwe we low to high-z [6, 7] 5ns notes: 4. test conditions assume signal transition time of 3 ns or less , timing reference levels of 1.5v, input pulse levels of 0 to 3. 0v. 5. t power gives the minimum amount of time that the power supply should be at stable, typical v cc values until the first memory access can be performed. 6. t hzoe , t hzce , and t hzwe are specified with a load capacitance of 5 pf as in part (d) of ac test loads. transition is measured when the outputs enter a high impedance state. 7. at any given temperature and voltage condition, t hzce is less than t lzce , t hzoe is less than t lzoe , and t hzwe is less than t lzwe for any given device. 8. the internal write time of the memory is defined by the overlap of ce low, and we low. ce and we must be low to initiate a write, and the transition of either of these signals can terminate the write. the input data set-up and hold timing should be referenced to the leading edge of the signal t hat terminates the write. 9. the minimum write cycle time for write cycle no. 3 (we controlled, oe low) is the sum of t hzwe and t sd . [+] feedback
cy7c1010dv33 document number: 001-00062 rev. *c page 6 of 12 data retention characteristics over the operating range [10] parameter description conditions min max unit v dr v cc for data retention 2v i ccdr data retention current v cc = v dr = 2.0v, ce > v cc ? 0.3v, v in > v cc ? 0.3v or v in < 0.3v 10 ma t cdr [11] chip deselect to data retention time 0 ns t r [ 12] operation recovery time t rc ns data retention waveform switching waveforms figure 4. read cycle no. 1 [13, 14] 3.0v 3.0v t cdr v dr > 2v data retention mode t r ce v cc previous data valid data valid rc t aa t oha t rc address data out notes 10. no inputs may exceed v cc + 0.3v 11. tested initially and after any design or proce ss changes that may affect these parameters. 12. full device operation requires linear v cc ramp from v dr to v cc(min.) > 50 ? s or stable at v cc(min.) > 50 ? s. 13. the device is continuously selected. oe , ce = v il . 14. we is high for read cycle. [+] feedback
cy7c1010dv33 document number: 001-00062 rev. *c page 7 of 12 figure 5. read cycle no. 2 (oe controlled) [14, 15] figure 6. write cycle no. 1 (we controlled, oe high during write) [16, 17] switching waveforms (continued) 50% 50% data valid t rc t ace t doe t lzoe t lzce t pu high impedance t hzoe t hzce t pd high oe ce i cc i sb impedance address data out v cc supply current t hd t sd t pwe t sa t ha t aw t sce t wc t hzoe data in valid ce address we data i/o oe note 18 notes 15. address valid before or similar to ce transition low. 16. data io is high impedance if oe = v ih . 17. if ce goes high simultaneously with we going high, the output remains in a high impedance state. 18. during this period, the i/os are in output state and input signals should not be applied. [+] feedback
cy7c1010dv33 document number: 001-00062 rev. *c page 8 of 12 figure 7. write cycle no. 2 (we controlled, oe low) [17] truth table ce oe we io 0 ?io 7 io 8 ?io 15 mode power h x x high-z high-z power down standby (i sb ) l l h data out data out read all bits active (i cc ) l x l data in data in write all bits active (i cc ) l h h high-z high-z selected, outputs disabled active (i cc ) switching waveforms (continued) data valid t hd t sd t lzwe t pwe t sa t ha t aw t sce t wc t hzwe ce address we data i/o note 18 [+] feedback
cy7c1010dv33 document number: 001-00062 rev. *c page 9 of 12 ordering information speed (ns) ordering code package diagram package type operating range 10 CY7C1010DV33-10vxi 51-85090 36-pin (400-mil) molded soj (pb-free) industrial CY7C1010DV33-10zsxi 51-85087 44-pin tsop ii (pb-free) ordering code definitions temperature range: i = industrial package type: xxx = vx or zsx vx = 36-pin (400-mil) molded soj (pb-free) zsx = 44-pin tsop ii (pb-free) speed: 10 ns v33 = voltage range (3 v to 3.6 v) d = c9, 90 nm technology 0 = data width 8-bits 01 = 2-mbit density 1 = fast asynchronous sram family technology code: c = cmos 7 = sram cy = cypress c cy 1 v33 - 10 xxx 7 01 0 d i [+] feedback
cy7c1010dv33 document number: 001-00062 rev. *c page 10 of 12 package diagrams figure 8. 36-pin (400-mil) molded soj (51-85090) 51-85090 *e [+] feedback
cy7c1010dv33 document number: 001-00062 rev. *c page 11 of 12 figure 9. 44-pin tsop ii (51-85087) package diagrams (continued) 51-85087 *c [+] feedback
document number: 001-00062 rev. *c revised october 14, 2010 page 12 of 12 all product and company names mentioned in this document are the trademarks of their respective holders. cy7c1010dv33 ? cypress semiconductor corporation, 2005-2010. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or ot her rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreemen t with cypress. furthermore, cypress does not authorize its products for use as critical components in life-support syst ems where a malfunction or failure may reas onably be expected to result in significa nt injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and international treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or impl ied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress re serves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. document history page sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representative s, and distributors. to find t he office closest to you, visit us at cypress.com/sales. products psoc psoc.cypress.com clocks & buffers clocks.cypress.com wireless wireless.cypress.com memories memory.cypress.com image sensors image.cypress.com psoc solutions general psoc.cypress.com/solutions low power/low voltage psoc.cypress.com/low-power precision analog psoc.cypress.com/precision-analog lcd drive psoc.cypress.com/lcd-drive can 2.0b psoc.cypress.com/can usb psoc.cypress.com/usb document title: cy7c1010dv33, 2-mbit (256k x 8) static ram document number: 001-00062 rev. ecn no. submission date orig. of change description of change ** 342195 see ecn pci new data sheet *a 459073 see ecn nxr converted preliminary to final. removed commercial operating range from product offering. removed -8 ns and -12 speed bin removed the pin definitions table. modified maximum ratings for dc input voltage from -0.5v to -0.3v and v cc + 0.5v to v cc + 0.3v changed i cc max from 65 ma to 90 ma changed the description of i ix from ?input load current? to ?input leakage current? updated the thermal resistance table. updated footnote #7 on high-z parameter measurement added footnote #12 updated the ordering information and replaced package name column with package diagram in the ordering information table. *b 2602853 11/07/08 vkn/pyrs added 36-pin soj package and its related information *c 3059211 10/14/2010 pras added ordering code definitions . updated package diagrams . [+] feedback

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